1. Field of the Invention
The present invention relates to a clock generating circuit for generating an internal clock signal synchronized with an external clock signal, and more particularly to an internal clock generating circuit for generating an internal clock signal used at least for outputting data in a synchronous-type semiconductor memory device. More specifically, the present invention is related to a circuit for adjusting a delay amount of a DLL (Delay Locked Loop) for generating an internal clock signal synchronized in phase with an external clock signal by delaying the external clock signal.
2. Description of the Background Art
A clock synchronous semiconductor memory device for transferring data/signal in synchronization with a clock signal is widely used. In the clock synchronous semiconductor memory device, a skew of a signal/data is required to be considered only with respect to the clock signal, and it is unnecessary to consider a skew among signals, so that an internal operation start timing can be advanced. For example, data is transferred synchronously with a clock signal as a system clock, high-speed data transfer can be achieved and a bandwidth of data transfer can be widened.
As a clock synchronous semiconductor memory device, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) for transferring data synchronously with the rising and falling edges of a clock signal is known.
FIG. 23 is a diagram showing data outputting timings of the DDR SDRAM. As shown in FIG. 23, output data Q0 to Q3 is successively outputted synchronously with the rising and falling edges of an external clock signal CLK. It is determined to output data DQ synchronously with the rising and falling edges of external clock signal CLK as a general standard of output timings of a DDR-SDRAM.
In the case of outputting data by using external clock signal CLK as a trigger, due to delay in a clock input buffer for generating an internal clock and a data output buffer for outputting data, output data is delayed with respect to external clock signal CLK, so that the general standard of data output cannot be satisfied.
Therefore, usually in a DDR-SDRAM, in order to generate a clock signal used for data output, a DLL (Delay Locked Loop) circuit is provided internally. The DLL circuit delays external clock signal CLK by using fixed delay and variable delay internally, thereby generating clock signals CLKP and CLKN for data output each leading in phase relative to external clock signal CLK.
FIG. 24 is a diagram schematically showing the general configuration of a conventional DLL circuit. In FIG. 24, a DLL circuit 900 is provided with a clock input buffer 890 for generating buffered clock signals BUFCLK and ZBUFCLK by buffering external complementary clock signals CLK and ZCLK.
DLL circuit 900 includes: an internal clock generating circuit 902 for generating internal clock signals CLKP and CLKN by delaying buffered clock signals BUFCLK and ZBUFCLK, respectively; a phase difference detecting circuit 904 for detecting a phase difference between internal clock signal CLKP and buffered clock signal BUFCLK and generating signals UP and DWN indicative of a detection result; and a phase control circuit 906 for controlling a delay amount of internal clock generating circuit 902 in accordance with phase detection signals UP and DWN from phase difference detecting circuit 904.
Internal clock signal CLKP for data output is fed back, the phase of internal clock signal CLKP is compared with the phase of buffered clock signal BUFCLK in phase difference detecting circuit 904, and a delay amount in internal clock generating circuit 902 is so adjusted as to minimize the phase difference. By adjusting the phase of internal clock signal CLKP for data output in consideration of delays in clock input buffer 890 and the data output buffer, the phase of external clock CLK and the phase of the data output can be made coincident with each other.
FIG. 25 is a diagram showing more specifically a configuration of DLL circuit 900 in FIG. 24. In FIG. 25, phase difference detecting circuit 904 includes: a replica buffer 34 for delaying internal clock signal CLKP by a predetermined time; and a phase detector 35 for detecting the phase difference between a feedback clock signal FBCLK outputted from replica buffer 34 and buffered clock signal BUFCLK. Replica buffer 34 is provided to compensate for the delays in clock input buffer 890 and the data output buffer shown in FIG. 24. Usually, clock input buffer 890 is constructed by a differential amplifier. In the case of detecting an intersecting portion of complementary external clock signals CLK and ZCLK and generating buffered clock signals BUFCLK and ZBUFCLK, the delay in clock input buffer 890 is neglected.
Phase detector 35 outputs phase detection result indicating signals UP and DWN in accordance with a result of phase comparison between feedback clock signal FBCLK and buffered clock signal BUFCLK. If feedback clock signal FBCLK leads in phase the buffered clock signal BUFCLK, up instruction signal UP is set to the H level in order to increase the delay amount of internal clock signals CLKP and CLKN. On the contrary, where feedback clock signal FBCLK lags in phase behind buffered clock signal BUFCLK, in order to advance the phases of internal clock signals CLKP and CLKN, down instruction signal DWN is set to the H level.
The delay amount of internal clock signal CLKP is increased by up instruction signal UP and is decreased by down instruction signal DWN.
Phase control circuit 906 includes: a counting circuit 307 for performing a counting operation in accordance with output signals UP and DWN of phase detector 35; and a count control circuit 41 for controlling the minimum count value of counting circuit 37 upon power up or system reset. According to a count A[N:0] of counting circuit 37, the delay amount of each of internal clock signals CLKP and CLKN is set.
Internal clock generating circuit 902 includes: a variable delay line 32 for generating internal clock signal CLKP by delaying buffered clock signal BUFCLK; and a variable delay line 33 for generating internal clock signal CLKN by delaying buffered clock signal ZBUFCLK. Count A[N:0] of counting circuit 37 is commonly supplied to variable delay lines 32 and 33. Count circuit 37 is a bidirectional counter. The count of counting circuit 37 is increased when up instruction signal UP outputted from phase detector 35 is activated, and is decreased when down instruction signal DWN outputted from phase detector 35 is activated. The delay amount of each of variable delay lines 32 and 33 is set by the count of counting circuit 37. When count A[N:0] increases, the delay amounts of variable delay lines 32 and 33 increase.
Count control circuit 41 controls the counting operation of counting circuit 37 by an enable signal EN. When enable signal EN is set to the H level, counting circuit 37 performs the counting operation. When enable signal EN is set to the L level, the counting operation is stopped. For example, in a power down mode or the like, the counting operation of counting circuit 37 is stopped to reduce current consumption.
FIGS. 26A and 26B are diagrams illustrating the phase detecting operation of phase detector 35 shown in FIG. 25. Phase detector 35 generates output signals UP and DWN so that the phase of feedback clock signal FBCLK and the phase of buffered clock signal BUFCLK coincide with each other. Signals UP and DWN are signals complementary to each other. The phase detection timing is the rising edge of buffered clock signal BUFCLK.
In FIG. 26A, if feedback clock signal FBCLK is at the L level at the rising edge of buffered clock signal BUFCLK, the phase of feedback clock signal FBCLK has to be advanced. In this case, therefore, down instruction signal DWN from phase detector 35 is set to the H level, and the delay amount of feedback clock signal FBCLK is reduced.
As shown in FIG. 26B, when feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal BUFCLK, the phase of feedback clock signal FBCLK is advanced relative to buffered clock signal BUFCLK. In this case, therefore, it is necessary to delay feedback clock signal FBCLK. By setting the up instruction signal UP to the H level, the delay amount of feedback clock signal FBCLK is increased.
FIGS. 27 and 28 are diagrams representing the operation of DLL circuit 900 shown in FIG. 25. Referring to FIGS. 27 and 28, a phase adjusting operation of DLL circuit 900 will be briefly described.
In FIG. 27, buffered clock signal BUFCLK rises to H level at time t1. Variable delay lines 32 and 33 delay buffered clock signals BUFCLK and ZBUFCLK, respectively, in accordance with the count from counting circuit 27.
In FIG. 27, internal clock signal CLKP rises to H level at time t2. Replica buffer 34 delays internal clock signal CLKP for data output by a predetermined time (predetermined fixed time). Therefore, feedback clock signal FBCLK rises to H level at time t3. In this case, the rising edge of feedback clock signal FBCLK occurs at a timing faster than the rising edge of buffered clock signal BUFCLK. Consequently, phase detector 35 sets the up instruction signal UP to the H level in order to increase the delay amount of internal clock signal CLKP.
Specifically, in DLL circuit 900, by delaying buffered clock signals BUFCLK and ZBUFCLK, internal clock signals CLKP and CLKN are generated. Feedback clock signal FBCLK is delayed by replica buffer 34 by fixed time. Therefore, the data output timing can be set to a timing faster than the rising edge of external clock signal CLK, and data can be outputted synchronously with the edge of external clock signal CLK.
By the phase adjusting operation, in FIG. 28, the rising edge of feedback clock signal FBCLK and that of buffered clock signal BUFCLK are made coincident with each other. In this case, at time t2 in FIG. 28, internal clock signal CLKP for data output goes high. Synchronously with internal clock CLKP, data output is executed. The delay time of replica buffer 34 is determined in consideration of delay time of data propagation in the data output buffer. Therefore, by outputting data synchronously with data outputting internal clock signals CLKP and CLKN at timings shown in FIG. 28, data is transferred via the output buffer between time t2 and t3, and the output data changes at time t3. Since clock signal CLKN is also generated similarly by delaying buffered clock signal ZBUFCLK, data can be outputted at the falling edge of external clock signal CLK. Thus, data can be outputted synchronously with the rising and falling edges of external clock signal CLK.
The number of cycles required until the phase of buffered clock signal BUFCLK and that of feedback clock signal FBCLK coincide with each other takes the maximum when after power-on reset, clock signals BUFCLK and FBCLK are out of phase by 180xc2x0 from each other, for example.
Specifically, as shown in FIG. 29, when buffered clock signal BUFCLK and feedback clock signal FBCLK are out of phase from each other by 180xc2x0 C., the phase of feedback clock signal FBCLK is determined to be either the H or L level at the rising edge of buffered clock signal BUFCLK. Each of clock signals BUFCLK and FBCLK is a clock signal of which duty is 50%, in which the H level period and the L level period are equal to each other. In this case, according to a result of the determination, when the phase of feedback clock signal FBCLK changes, in the subsequent cycles, the signal UP or DWN is successively generated until the phases coincide with each other.
Assuming that the cycle of external clock signal CLK, that is, buffered clock signal BUFCLK is TCK(ns) and a delay amount of feedback clock signal FBCLK per cycle is xcex94t(ns), in the case of the 180xc2x0 out of phase, the number of cycles necessary to make the phases coincide with each other is given by (TCK/2)/xcex94t.
When it is assumed that the maximum value TCKmax of the clock cycle determined in specifications compliant with JEDEC (Joint Electron Device Engineering Council) is 15 ns and the delay amount xcex94t of one cycle is 0.04 ns, 187 cycles are necessary for the phase coincidence. On the other hand, the specification value of the maximum cycle number required for the DLL circuit to make the phases coincide with each other since the power-on resetting is 200. Therefore, in the case of comparing the phases with the duty ratio of feedback clock signal FBCLK maintained at 50%, the margin becomes extremely small with respect to the specification value. It would be possible that data cannot be outputted synchronously with the external clock signal stably at a faster timing after the power-on resetting.
In order to avoid the problem of synchronization or locking of the DLL circuit, a technique of waveform-shaping the data outputting clock signal into a self timing pulse having a predetermined pulse width of, for example, about 2 ns and feeding back the self timing pulse for phase comparison is used.
FIG. 30 is a diagram schematically showing the configuration of DLL circuit 900 including a self timing pulse generating circuit. In FIG. 30, in internal clock generating circuit 902, one-shot pulse generating circuits 39 and 40 are provided in output stages of variable delay lines 32 and 33, respectively. From one-shot pulse generating circuits 39 and 40, internal clock signals CLKP and CLKN for data output are generated, respectively. Internal clock signal CLKP outputted from one-shot pulse generating circuit 39 is supplied to replica buffer 34 in phase difference detecting circuit 904.
The other configuration of the DLL circuit shown in FIG. 30 is the same as that of the DLL circuit shown in FIG. 25, the same reference numerals are designated to corresponding parts and their detailed description will not be repeated.
One-shot pulse generating circuit 39 generates a one-shot pulse signal set to L level for a predetermined time in response to the rising of the output clock signal CLKPF of variable delay line 32 as shown in FIG. 31. The output pulse of one-shot pulse generating circuit 39 is fed back as feedback clock signal FBCLK to phase detector 35 via replica buffer 34.
Count control circuit 41 sets predetermined bits in an enable signal EN[N:0] to the L level until down instruction signal DWN is generated from phase detector 35 and increases the count step of counting circuit 37 to be larger than the minimum value. When down instruction signal DWN is generated, count control circuit 41 sets all bits of enable signal EN[N:0] to the H level. Accordingly, the delay change amount per one cycle is set to the minimum value when the delay amount decreases.
FIG. 32 is a diagram schematically showing the phase relation of feedback clock signal FBCLK and buffered clock signal BUFCLK. Feedback clock signal FBCLK has an L-level period of a predetermined period (for example, 2 ns) by one-shoe pulse generating circuit 39.
Assuming now that the falling edge of feedback clock signal FBCLK is generated substantially at the same timing as the rising edge of buffered clock signal BUFCLK. When phase detector 35 determines that feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal BUFCLK, phase detector 35 sets the up instruction signal UP to the H level to increase a delay amount. In this case, therefore, the feedback clock signal FBCLK is required to have the phase thereof shifted by the H level period thereof . On the other hand, when it is determined that feedback clock signal FBCLK is at the L level at the rising edge of buffered clock signal BUFCLK, down instruction signal DWN is set to the H level and a delay amount is decreased. In this case, therefore, the delay amount is adjusted only by the L level period of feedback clock signal FBCLK.
The L level period of feedback clock signal FBCLK is short as, for example, 2 ns and the H level period is long. Consequently, in the beginning of the phase adjustment, when feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal FUBCLK, a delay change amount per cycle is set to, for example, 8 xcex94t. When feedback clock signal FBCLK goes low for the first time and down instruction signal DWN responsively goes high after resetting of DLL circuit 900, the delay change amount of a delay cycle of each of variable delay lines 32 and 33 is reduced to At. In this case, when the cycle of buffered clock signal BUFCLK is TCK and the L level period of feedback clock signal FBCLK is 2 ns, the maximum number of cycles until the phases coincide with each other is expressed by the following expression.
(TCKxe2x88x922)/(8 xcex94t)+2/xcex94t
Where the cycle TCK is 15 ns and the minimum delay change amount xcex94t is 0.04 ns, the maximum number of cycles required for the phase coincidence is about 90 cycles. The margin can be largely increased as compared with 200 cycles defined in the specification value of JEDEC.
FIG. 33 is a diagram schematically showing the configuration of count control circuit 41 shown in FIG. 30. In FIG. 33, count control circuit 41 includes an interconnection 41a for fixing enable signals EN[N:3] to the H level (power supply voltage VDD level) and a set/reset flip flop 41b which is reset in response to a power-on detection signal (power-on reset signal) ZPOR and is set in response to activation of down instruction signal DWN to generate enable signals EN[2:0].
In the configuration of count control circuit 41 shown in FIG. 33, after power on, all of enable signals EN[N:3] are fixed to the H level. On the other hand, set/reset flip flop 41b is reset by power-on detection signal ZPOR after power up to set enable signals EN[2:0] to the L level. When down instruction signal DWN is set to the H level, set/reset flip flop 41b is set, thereby setting enable signals EN[2:0] to the H level.
FIG. 34 is a diagram schematically showing the configuration of counting circuit 37 shown in FIG. 30. In FIG. 34, counting circuit 37 includes (N+1) unit counters CNT0 to CNTN. From unit counters CNT0 to CNTN, delay setting signals (delay stage address signals) A[0] to A[N] are generated. To unit counters CNT0 to CNTN, up instruction signal UP and down instruction signal DWN are supplied. Enable signals EN[0] to EN[N] are supplied to unit counters CNT0 to CNTN, respectively. Unit counters CNT0 to CNTN execute counting operation when corresponding enable signals EN[0] to EN[N] are set to the H level.
Therefore, since enable signals EN[2:0] are at the L level until down instruction signal DWN is activated after power on, unit counters CNT0 to CNT2 do not perform the counting operation, and delay stage address signals A[0] to A[2] are maintained at the initial values. Unit counters CNT3 to CNTN perform the counting operation in accordance with up instruction signal UP and increase their count values.
By delay stage address signal bits A[0:N], the delay amounts of variable delay lines 32 and 33 shown in FIG. 30 are set. The counting operation is performed by the unit counters of and upper than counter CNT3, and the count bits of and upper than bit A[3] (delay stage address signals) change. Therefore, delay stage address signals A[N:0] indicate the delay amount of the variable delay circuit in a binary number notation, and the delay amount is changed in a unit of 8 xcex94t. The configuration of variable delay lines 32 and 33 will be described later. Delay stages having delay amounts according to weights of counter bits A[0] to A[N] are cascaded, a corresponding delay stage is selectively bypassed according to the values of count bits A[0] to A[N], and a delay amount of the variable delay line is set.
When feedback clock signal FBCLK is set to the H level at the rising edge of buffered clock signal BUFCLK and up instruction signal UP is set to the H level, the counting operation is performed by count bits A[3:N], and a delay amount is increased in a step of 8 xcex94t. When down instruction signal DWN is set to the H level, enable signal EN[2:0] is set to the H level, and the counting operation is performed by using count bits A[0] to A[N] of counting circuit 37. In this case, therefore, the delay amount of variable delay lines 32 and 33 is changed in a step of xcex94t.
When the phase of buffered clock signal BUFCLK and that of feedback clock signal FBCLK become close to each other, there is the possibility that an output signal of phase detector 35 enters a metastable state. When the output signal of phase detector 35 enters the metastable state, count bits A[N:0] of counting circuit 37 also enter the metastable state, and the number of delay stages used in variable delay lines 32 and 33 becomes undetermined. Therefore, internal clock signals CLKP and CLKN also become indefinite and there is the possibility that the data output timing cannot be synchronized with external clock signal CLK.
FIG. 35 is a diagram showing a further configuration of a conventional DLL circuit. In DLL circuit 900 shown in FIG. 35, to reduce the probability that an influence of the metastable state of an output signal of phase detector 35 is exerted on the number of delay stages used in variable delay lines 32 and 33, an output signal of phase detector 35 is transmitted to counting circuit 37 via a shifting circuit 42. An output signal of phase detector 35 is transmitted to counting circuit 37 via shifting circuit 42. Therefore, there is time lag by the shift circuit 42 from when feedback clock signal FBCLK falls for the first time at the rising edge of buffered clock signal BUFCLK and until when the delay is actually is decreased subsequently. In the period of the time lag, where the number of stages of shifting circuit 42 is M, a delay amount erroneously increase by Mxc3x97(8 xcex94t). For example, when a variable delay amount per cycle immediately after feedback clock signal FBCLK falls to L level for the first time at the rising edge of buffered clock signal BUFCLK is xcex94t and the number of shifting stages of shifting circuit 42 is three, 24 cycles are necessary to compensate for the excessive increase in the delay amount.
To prevent excessive control by such a time lag, count control circuit 41 is provided with the function of compensating for the excessive increase in the delay amount.
FIG. 36 is a diagram showing an example of the configuration of count control circuit 41. In FIG. 36, count control circuit 41 includes: an inverter 41c receiving down instruction signal DWN; an NOR circuit 41d receiving enable signal EN and an output signal of inverter 41c; an AND circuit 41e receiving buffered clock signal BUFCLK and an output signal of NOR circuit 41d; a shifter 41f for performing an internal transferring operation when a signal supplied to an input IN is at the H level and outputting an internal signal to an output OUT when the signal supplied to input IN is at the L level; a shifter 41g receiving an output signal of shifter 41f by input IN; and an AND circuit 41h receiving output signals of shifters 41f and 41g and generating enable signals EN[2:0].
AND circuit 41h outputs a 1-bit signal, and enable signals EN[2:0] are commonly controlled by AND circuit 41h. To a reset input RST in each of shifters 41f and 41g, a reset signal RESET is applied. Reset signal REST is set to the H level at the time of power-on reset or at the time of system reset.
FIG. 37 is a diagram showing an example of the configuration of shifters 41f and 41g shown in FIG. 36. Since shifters 41f and 41g have the same configuration, the configuration of one shifter is representatively shown in FIG. 37.
In FIG. 37, each of shifters 41f and 41g includes: a reset transistor TR0 for resetting an internal node F0 to the ground voltage level in accordance with a reset signal applied to reset input RST; an inverter IV0 for inverting a signal at internal node F0; a tri-state buffer TB0 activated when a signal applied to input IN is at the L level and transmitting an output signal of inverter IV0 when activated; an inverter latch LT0 for inverting and latching an output signal of tri-state buffer TB0; a tri-state buffer TB1 activated when a signal applied to input IN is at the H level, and inverting and transmitting the latch signal of latch LT0 when activated; an inverter latch LT1 for latching an output signal of tri-state buffer TB1; a tri-state buffer TB2 activated when a signal applied to input IN is at the L level, and inverting the latch signal of latch LT1 for transmission to an output node OUT; and an inverter latch LT3 for latching an output signal of tri-state buffer TB2.
A signal applied to input IN is inverted by an internal inverter, and complementary signals of inputs IN and ZIN are applied as control signals to tri-state buffers TB0 to TB2.
FIG. 38 is a timing chart representing the operation of count control circuit 41 shown in FIGS. 36 and 37. Referring to FIG. 38, the operation of the count control circuit shown in FIGS. 36 and 37 will be described below.
In the initial state, shifters 41f and 41g are set by reset signal RESET applied to reset input RST, and internal node F0 is set to the L level. Since the down instruction signal DWN is at the L level, an output signal of inverter 41c is at the H level and an output signal of NOR circuit 41d is accordingly at the L level. An output signal of AND circuit 41e is at the L level. In shifter 41f, tri-state buffer TB2 at the output stage is in an active state and a signal of the L level is outputted. Similarly, an output signal F002 of shifter 41g is at the L level. In this state, enable signals EN[2:0] are at the L level.
By the shifting operation of shifting circuit 42, even when buffered clock signal BUFCLK is generated during a period in which down instruction signal DWN is at the L level, an output signal of AND circuit 41e is at the L level. In each of shifters 41f and 41g, tri-state buffer TB1 is in an output high impedance state, a transferring operation is not internally performed, and all of enable signals EN[2:0] maintain at the L level.
When down instruction signal DWN rises to the H level by the shifting operation of shifting circuit 42, an output signal of inverter 41c goes low. Accordingly, an output signal of NOR circuit 41d attains the H level. When buffered clock signal BUFCLK goes high, an output signal of AND circuit 41e goes high, tri-state buffer TB1 is activated in shifter 41f, and the L-level signal latched by latch LT0 is transferred to latch LT1. In this state, tri-state buffer TB2 is in an output high impedance state, and a signal F001 from output node OUT maintains the L level.
When buffered clock signal BUFCLK falls to the L level, tri-state buffer TB1 enters an output high impedance state. On the other hand, tri-state buffers TB0 and TB2 are activated, the H-level signal latched by latch LT1 is outputted to output node OUT, and output signal F001 of shifter 41f attains the H level. The L-level signal is transferred to latch LT0 by inverter IV0, and latch LT0 maintains the output signal at the H level.
In shifter 41g, when output signal F001 of shifter 41f rises, the transferring operation is performed internally, and the signal latched by latch LT1 rises to the H level.
In the following cycle, if down instruction signal DWN maintains the H level, shifter 41f performs the internal transferring operation again in response to the rising edge of buffered clock signal BUFCLK, thereby transferring the H-level signal latched by latch LT0 to latch LT1. When buffered clock signal BUFCLK goes low, tri-state buffer TB2 is accordingly activated, and output signal F001 of output node OUT falls to L level.
When output signal F001 of shifter 41f falls to the L level, tri-state buffer TB2 in the final stage of shifter 41g is activated, the H-level signal latched by latch LT1 is transferred to output node OUT, and output signal F002 of output node OUT rises to the H level. Even when output signal F002 of shifter 41g goes high, output signal F001 of shifter 41f remains at the L level, and an output signal of AND circuit 41h is at the L level. Therefore, enable signal EN[2:0] is still maintained at the L level.
Where down instruction signal DWN is set at the H level, the transferring operation is performed again in shifter 41f in response to the rising edge of buffered clock signal BUFCLK. In response to the falling edge of buffered clock signal BUFCLK, output signal F001 of shifter 41f goes high.
In shifter 41g, when output signal F001 of shifter 41f is at the L level, the internal transferring operation is not performed, and the latching state is maintained. Therefore, output signal F002 of shifter 41g is maintained at the H level. When the output signal of shifter 41f rises to the H level, tri-state buffer TB1 is activated in shifter 41g, and the signal latched in latch LT0 is transferred to latch LT1. In this state, however, tri-state buffer TB2 is in the output high impedance state, and the H-level signal latched by latch LT3 is outputted. Therefore, when output signal F001 of shifter 41f goes high, output signal F001 of shifter 41g is at the H level, and an output signal of AND circuit 41h, that is, enable signals EN[2:0] rise to the H level.
When enable signals EN[2:0] go high, the output signal of NOR gate 41d is fixed at the L level, the shifting operation in shifters 41f and 41g is not performed and, hereinafter, enable signals EN[2:0] are maintained at the H level.
Therefore, when down instruction signal DWN is generated three times in total, enable signals EN[2:0] are set to the H level, and the counting of counting circuit 37 is executed by using all bits A[N:O].
Where shifting circuit 42 is constructed by shifters of three stages, the delay amount increases three due to the time lag caused in the shifting operation of shifting circuit 42, the number of delay stages is decreased three times in total, and then the delay change amount per cycle is set to the minimum unit of xcex94t. Consequently, when shifting circuit 42 is constructed by shifters of N stages, in count control circuit 41, as shifters 41f and 41g, shifters of (Nxe2x88x921) stages are provided. According to output signals of the shifter in the final stage and the shifter in the preceding stage of the final stage, enable signals EN[2:0] are generated.
The shifters of M stages in shifting circuit 42, and the delay change amount per cycle is assumed to be nxcex94t until the feedback clock signal FBCLK falls to the L level for the first time after resetting of the DLL circuit at the timing of the rising edge of buffered clock signal BUFCLK, and the L level period width of feedback clock signal FBCLK is assumed to be AT. Under such assumption, in order to compensate for the excessive delay increase amount, the following inequality has to be satisfied.
xe2x80x83xcex94T greater than Mxc2x7nxcex94t
When the inequality is satisfied, the delay amount is decreased by M times for the excessive delay increase of M times, so that no problem occurs. However, if due to variations in processes or the like, the self timing pulse width xcex94T of feedback clock signal FBCLK is shortened, there is caused the possibility that the above inequality does not hold. The case where the number of stages of shifters of shifting circuit 42 is three (M=3) will now be considered.
FIG. 39 is a diagram schematically showing the configuration of a DLL circuit in which shifters of three stages are provided in shifting circuit 42. In phase difference detecting circuit 904 shown in FIG. 39, shifters 42ua to 42uc of three stages for transferring an output signal UP0 of phase detector 35 synchronously with buffered clock signal BUFCLK, and shifters 42da to 42dc for transferring an output signal DWN0 of phase detector 35 synchronously with buffered clock signal BUFCLK are provided. Output signals UP and DWN of shifters 42uc and 42dc are applied as an up instruction signal and a down instruction signal, respectively, to counting circuit 37. Down instruction signal DWN is also applied to count control circuit 41.
Each of shifters 42ua to 42uc and shifters 42da to 42dc latches the applied signal in response to buffered clock signal BUFCLK and an output signal of the circuit of the preceding stage and outputs the latched signal synchronously with the falling edge of buffered clock signal BUFCLK. Signals UP and DWN outputted from shifters 42uc and 42dc therefore change synchronously with the falling edge of buffered clock signal BUFCLK.
FIG. 40 is a diagram illustrating the phase adjusting operation of the DLL circuit shown in FIG. 39. A case where the L level period of feedback clock signal FBCLK is delayed to start behind the falling edge of buffered clock signal BUFCLK before the number of delay stages is decreased three times in total will now be considered. A case where the L level period (self timing width) of feedback clock signal FBCLK is Al and smaller than 3xc3x978 xcex94t will be considered.
In clock cycle number 0, all of output signals UP0 to UP2 of shifters 42ua to 42uc and output signal UP are at the H level. In this state, up instruction signal UP is at the H level, the delay amount of feedback clock signal FBCLK is increased by 8 xcex94t, and the phase of feedback clock signal FBCLK is delayed.
By the phase adjusting operation, in clock cycle number 1, feedback clock signal FBCLK is set at L level at the rising edge of buffered clock signal BUFCLK. However, up instruction signal UP is at the H level, so that the delay amount of feedback clock signal FBCLK is increased by 8 xcex94t again. Subsequently, the operation is successively performed until clock cycle number 3.
Therefore, in clock cycle number 4, although feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal BUFCLK, up instruction signal UP falls to L level for the first time. Consequently, the delay amount of feedback clock signal FBCLK is decreased by 8 xcex94t.
In the following clock cycle as well, up instruction signal UP is at the L level, so that the delay amount of feedback clock signal FBCLK is decreased by 8 xcex94t again. In clock cycle number 6, although feedback clock signal FBCLK is at the L level at the rising edge of buffered clock signal BUFCLK, up instruction signal UP from shifter 42uc is at the H level, so that the delay amount is increased again. In this case, output signal UP0 of phase detector 35 falls to the L level (signal DWN0 is at the H level).
Therefore, since feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal BUFCLK in clock cycle numbers 3 to 5, so that the delay amount is increased over three clock cycles 6 to 8 successively.
When feedback clock signal FBCLK is delayed in clock cycle 6, feedback clock signal FBCLK has the same phase relation as in clock cycle number 5 with respect to buffered clock signal BFCLK, and the phase adjustment is performed beyond the L level period of feedback clock signal FBCLK. That is, the phase adjustment is performed exceeding the L level period, so that the phase compensation is executed excessively.
In clock cycle number 9, since up instruction signal UP goes low in accordance with output signal UP0 of phase detector 35 in clock cycle number 6, the phase delay amount of feedback clock signal FBCLK is decreased by 8 xcex94t. Since down instruction signal DWN is activated three times in total, the phase adjustment unit in the subsequent cycles are set to xcex94t.
Up instruction signal UP and down instruction signal DWN are complementary signals so that when up instruction signal UP is at the L level, down instruction signal DWN is at the H level. In this case, therefore, count control circuit 41 sets all of enable signals EN[2:0] to the H level in accordance with the down instruction signal (the L level of up instruction signal UP) of the third time in clock cycle number 9, so that the delay change amount per cycle of clock cycle number 10 changes to the minimum unit of xcex94t.
From clock cycle number 7, feedback clock signal FBCLK is at the H level at the rising edge of buffered clock signal BUFCLK, so that signal UP0 outputted from phase detector 35 is at the H level from the clock cycle 7. Accordingly, up instruction signal UP outputted from shifter 42uc rises to the H level again from clock cycle number 10.
In clock cycle number 10, the delay amount has to be further increased according to the result of phase detection in clock cycle number 7. Since feedback clock signal FBCLK is at H level at the rising edge of buffered clock signal BUFCLK thereafter, a process of delaying the rising edge of feedback clock signal FBCLK to the next rising edge of buffered clock signal BUFCLK to establish a phase synchronization of buffered clock signal BUFCLK with the rising edge of feedback clock signal FBCLK is performed.
The sum of the L level period and the H level period of feedback clock signal FBCLK is equal to the cycle TCK of buffered clock signal BUFCLK. Therefore, in the delay adjusting operation in clock cycle number 10 and subsequent cycles, the delay amount has to be increased to the next rising edge of buffered clock signal BUFCLK by delay amount xcex94t of the minimum step.
As described above, when the L level period of the self timing pulse signal is shortened due to variations in processes and other(s) and becomes smaller than the product of the number of shifting stages and the delay change amount, an increase in the delay amount caused by the time lag in the shifting stages cannot be compensated for, and such a problem arises that the number of cycles necessary to lock feedback clock signal FBCLK with buffered clock signal BFCLK significantly increases.
An object of the present invention is to provide a clock generating circuit capable of synchronizing the phase of an internal clock signal with the phase of an external clock signal at high speed even when variations in process and other (s) generate.
Another object of the present invention is to provide a DLL circuit capable of suppressing an increase in the number of clock cycles necessary to establish the synchronization even when variations in process generate.
A clock generating circuit according to a first aspect of the present invention includes: an internal clock generating circuit for generating an internal clock signal in accordance with an external clock signal; a phase difference detecting circuit for detecting a phase difference between the internal clock signal and the external clock signal; a phase relation adjusting circuit for continuously maintaining a predetermine state for a predetermined number of clock cycles and, after the predetermined number of clock cycles, releasing the maintained predetermined state, when a phase relation between the internal clock signal and the external clock signal becomes the predetermined state,; a phase adjusting circuit for adjusting a phase of the internal clock signal in accordance with an output signal of the phase relation adjusting circuit; and a delay control circuit for setting a phase adjustment step of the phase adjusting circuit to a first delay amount until the number of the clock cycles maintaining the predetermined state of the phase adjusting circuit reaches the predetermined number of cycles and, setting the phase adjustment step of the phase adjusting circuit to a second delay amount smaller than the first delay amount when the number of the clock cycles of the predetermined state reaches the predetermined number of cycles.
A clock generating circuit according to a second aspect of the present invention includes: an internal clock generating circuit for generating an internal clock signal in accordance with an external clock signal; a phase difference detecting circuit for detecting a phase difference between the internal clock signal and the external clock signal; a phase adjusting circuit for adjusting a phase difference between the internal clock signal and the external clock signal in accordance with an output signal of the phase difference detecting circuit; and a delay control circuit for adjusting a phase adjustment step of the phase adjusting circuit in accordance with the output signal of the phase difference detecting circuit. The delay control circuit increases the phase adjustment step from a first value to a second value for a predetermined cycle period in response to a predetermined state instruction of an output signal of the phase difference detecting circuit and sets the phase adjustment step to a minimum value which is smaller than the first value in cycles after the predetermined period of the cycles.
A clock generating circuit according to a third aspect of the present invention includes: an internal clock generating circuit for generating an internal clock signal in accordance with an external clock signal; a phase difference detecting circuit for detecting a phase difference between the internal clock signal and the external clock signal; a phase adjusting circuit for adjusting a phase difference between the internal clock signal and the external clock signal in accordance with an output signal of the phase difference detecting circuit; and a delay control circuit for adjusting a phase adjustment step of the phase adjusting circuit in accordance with an output signal of the phase difference detecting circuit. The delay control circuit initializes the phase adjustment step to a first value larger than a minimum value and sets the phase adjustment step to the minimum value in response to release of the predetermined state of the output signal of the phase difference detecting circuit.
When the phase adjusting circuit is in a predetermined state, the predetermined state is continuously maintained for the predetermined number of clock cycles and the phase adjustment step is increased during such period, thereby enabling a delay amount which is excessively adjusted to the delay side to be compensated for with reliability.
By increasing the phase adjustment step when the predetermined state is detected in the phase difference detecting circuit, the delay change amount can be increased only in the predetermined state, and the delay amount which is excessively adjusted in the opposite direction can be compensated for with reliability.
By increasing the phase adjustment step in response to the predetermined state of the phases of the internal and external clock signals and setting the phase adjustment step to the minimum value in response to cancellation of the predetermined state, after reliably compensating for the delay amount excessively changed, the delay amount adjustment can be performed in a unit of the minimum delay amount adjustment step. Thus, the phases of external and internal clock signals can be synchronized with each other at high speed. Even when a process parameter and other (s) vary, the internal clock signal can be locked with the external clock signal with reliability at high speed after power is on.